The present subject matter generally concerns improved termination features for multilayer electronic components, and more particularly relates to via connections for multilayer capacitors. Specific formation and arrangement of internal electrode layers with an optional window termination layer facilitates the formation of low-inductance terminations. Such terminations are preferably compatible with ball grid array (BGA) and other device mounting technologies.
Many modern electronic components are packaged as monolithic devices, and may comprise a single component or multiple components within a single chip package. One specific example of such a monolithic device is a multilayer capacitor or capacitor array, and of particular interest with respect to the disclosed technology are multilayer capacitors with interdigitated internal electrode layers and corresponding electrode tabs. Examples of multilayer capacitors that include features of interdigitated capacitor (IDC) technology can be found in U.S. Pat. No. 5,880,925 (DuPré et al.) and U.S. Pat. No. 6,243,253 B1 (DuPré et al.). Other monolithic electronic components correspond to devices that integrate multiple passive components into a single chip structure. Such an integrated passive component may provide a selected combination of resistors, capacitors, inductors and/or other passive components that are formed in a multilayered configuration and packaged as a monolithic electronic device.
Selective terminations are often required to form electrical connections for various monolithic electronic components. Multiple terminations are needed to provide electrical connections to the different electronic components of an integrated monolithic device. Multiple terminations are also often used in conjunction with IDC's and other multilayer arrays in order to reduce undesirable inductance levels. One exemplary way that multiple terminations have been formed in multilayer components is by drilling vias through selected areas of a chip structure and filling the vias with conductive material such that an electrical connection is formed among selected electrode portions of the device.
Yet another way that terminations have been formed for multilayer electronic devices involves coating portions of termination lands with a solder stop material, thus forming a predefined area to which a solder ball or other solder preform may be applied.
Termination features for monolithic electronic components may also be designed such that small components are adapted for mounting to a relatively larger circuit board environment, such as in U.S. Pat. No. 6,324,048 B1 (Liu). Such is especially true for capacitor devices, with which it is often preferred to have very small devices positioned in a very specific location on a printed circuit board or other substrate. Thus, particular arrangement of internal and external component features may yield additional advancements in component configuration and termination. The disclosures of all of the foregoing mentioned patents are hereby incorporated by reference for all purposes.
While various aspects and alternative features are known in the field of capacitor formation and terminations therefor, no one design has emerged that generally addresses all of the issues as discussed herein.